Senior Mask Design Engineer
A company is looking for a Senior Mask Design Engineer. Key Responsibilities Perform physical layout of SRAM and datapath circuits using Cadence tools Engage in floor-planning, hierarchical layout assembly, and custom layout design Collaborate with circuit engineers to establish layout design methodologies Required Qualifications Bachelor's Degree or equivalent experience 3+ years' proven experience in memory macro layout Strong background in tight pitch related layout design Knowledge of the latest FinFET technology nodes and design rules Strong proficiency in layout tools, preferably Cadence Virtuoso
