Analog Layout Engineer

A company is looking for an Analog Layout Engineer responsible for designing high-performance analog cores. Key Responsibilities Lead the IC layout of high-performance analog cores including ADCs, DACs, PLLs, and transceivers Utilize industry best practices for layout in various CMOS process nodes from 5nm to 65nm Set up and debug LVS, DRC, and ERC environments using EDA tools Required Qualifications Thorough knowledge of EDA tools from Cadence, Mentor, and Synopsys 10+ years of experience in high-performance analog layout in advanced CMOS processes Experience with layout techniques such as common centroid layout and thermal-aware layout Familiarity with FinFET process nodes is preferred Experience in layout automation and skill code is a plus

Feb 14, 2025 - 18:10

A company is looking for an Analog Layout Engineer responsible for designing high-performance analog cores. Key Responsibilities Lead the IC layout of high-performance analog cores including ADCs, DACs, PLLs, and transceivers Utilize industry best practices for layout in various CMOS process nodes from 5nm to 65nm Set up and debug LVS, DRC, and ERC environments using EDA tools Required Qualifications Thorough knowledge of EDA tools from Cadence, Mentor, and Synopsys 10+ years of experience in high-performance analog layout in advanced CMOS processes Experience with layout techniques such as common centroid layout and thermal-aware layout Familiarity with FinFET process nodes is preferred Experience in layout automation and skill code is a plus