Senior UVM Verification Engineer
A company is looking for a Senior UVM Verification Engineer. Key Responsibilities Generate detailed UVM models to meet program verification requirements Create and execute test plans while meeting documentation needs per DO-254 guidelines Coordinate and direct team members in the verification effort and interface with customers for status updates Required Qualifications Bachelor's degree in Electrical or Computer Engineering, advanced degree preferred 6+ years of experience in designing and developing verification artifacts for FPGAs/ASICs Extensive experience with UVM Test Bench creation and DO-254 verification environment Strong knowledge of industry-standard verification tools and methodologies Aerospace experience is required
